1. Field of the Invention
The present invention relates to a voltage level shifter, and in particular to a voltage level shifter for a liquid crystal display to reduce power consumption when the level of an input signal is switched.
2. Description of the Related Art
FIG. 1 shows a schematic diagram of a conventional liquid crystal display system (hereinafter, referred to as an “LCD system”). The LCD system comprises a display area 10, a gate driver 11, a data driver 12, a voltage level shifter 13, and a timing controller 14. The voltage level shifter 13 receives low-level timing signals from the timing controller 14. In order to allow back-end components to correctly read the timing signals, the voltage level shifter 13 raises levels of the timing signals. Then, the raised timing signals are output from the voltage level shifter 13. According to the raised timing signals, the gate driver 11 and the scan driver 12 are driven to display images in the display area 10.
Generally, there are two circuit types for voltage level shifters as shown in FIG. 2 and FIG. 3. The major distinction is the location at which an input signal is input into each of the two circuit types for level shifters. Referring to the voltage level shifter 20 of FIG. 2, an input signal Vin20 is input to a gate of a NMOS transistor N20, and an input signal XVin20, inverse to the input signal Vin20, is input to a gate of a NMOS transistor N21. Since a operational time of the voltage level shifter 20 exceeds that of the voltage level shifter 30, the voltage level shifter 30 is always used to shift levels of signals.
Referring to the voltage level shifter 30 of FIG. 3, an input signal Vin30 is input to a source of a NMOS transistor N30, and an input signal XVin30, inverse to the input signal Vin30, is input to a source of a NMOS transistor N31. In the level shifter 3, sources of the PMOS transistors P30 and P31 are coupled to a voltage source VDD30 having a high voltage level. Since gates of the transistors N30 and N31 are both coupled to the voltage source VDD30, the transistors N30 and N31 remain turned on. When the input signal Vin30 remains at a low voltage level while input signal XVin30 remains at a high voltage level, a PMOS transistor P30 is turned off and a PMOS transistor P31 is turned on.
At this time, because a voltage level of the voltage source VDD30 is not equal to that of the input signal XVin30, a direct current path is formed between the sources of the PMOS transistor P31 and the NMOS transistor N31. The direct current path increases power consumption of the LCD system and reduces thin film transistors within the display area 10.